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| DM74S74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs August 1986 Revised April 2000 DM74S74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Ordering Code: Order Number DM74S74M DM74S74N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Function Table Inputs PR L H L H H H CLR H L L H H H CLK X X X L D X X X H L X Q H L H* H L Q0 Outputs Q L H H* L H Q0 H = HIGH Logic Level X = Either LOW or HIGH Logic Level L = LOW Logic Level = Positive-going Transition * = This configuration is nonstable; that is, it will not persist when either the preset and/or clear inputs return to its inactive (HIGH) level. Q0 = The output logic level of Q before the indicated input conditions were established. (c) 2000 Fairchild Semiconductor Corporation DS006457 www.fairchildsemi.com DM74S74 Absolute Maximum Ratings(Note 1) Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0C to +70C -65C to +150C Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL fCLK fCLK tW Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 2) Clock Frequency (Note 3) Pulse Width (Note 2) Clock HIGH Clock LOW Clear LOW Preset LOW tW Pulse Width (Note 3) Clock HIGH Clock LOW Clear LOW Preset LOW tSU tSU tH tH TA Setup Time (Note 2)(Note 4) Setup Time (Note 3)(Note 4) Input Hold Time (Note 2)(Note 4) Input Hold Time (Note 3)(Note 4) Free Air Operating Temperature 0 0 6 7.3 7 7 8 9 9 9 3 3 2 2 0 70 ns ns ns ns C ns ns 110 95 Parameter Min 4.75 2 0.8 -1 20 75 65 Nom 5 Max 5.25 Units V V V mA mA MHz MHz Note 2: CL = 15 pF, R L = 280, TA = 25C and VCC = 5V. Note 3: CL = 50 pF, R L = 280, TA = 25C and VCC = 5V. Note 4: The symbol () indicates the rising edge at the clock pulse is used for reference. www.fairchildsemi.com 2 DM74S74 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage HIGH Level Input Current Conditions VCC = Min, II = - 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIH = Min, VIL = Max VCC = Max VI = 2.7V D Clear Preset Clock IIL LOW Level Input Current VCC = Max VI = 0.5V (Note 6) IOS ICC Short Circuit Output Current Supply Current VCC = Max (Note 7) VCC = Max, (Note 8) D Clear Preset Clock -40 30 2.7 3.4 0.5 1 50 150 100 100 -2 -6 -4 -4 -100 50 mA mA mA A Min Typ (Note 5) Max -1.2 Units V V V mA Input Current @ Max Input Voltage VCC = Max, VI = 5.5V Note 5: All typicals are at VCC = 5V, TA = 25C. Note 6: Clear is tested with preset HIGH and preset is tested with clear HIGH. Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 8: With all outputs OPEN, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock is grounded. Switching Characteristics at VCC = 5V and TA = 25C RL = 280 Symbol Parameter From (Input) To (Output) fMAX tPLH tPLH tPHL Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output (Clock HIGH) tPHL Propagation Delay Time HIGH-to-LOW Level Output (Clock LOW) tPHL Propagation Delay Time HIGH-to-LOW Level Output (Clock HIGH) tPHL Propagation Delay Time HIGH-to-LOW Level Output (Clock LOW) tPLH tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Clock to Q or Q 9 12 ns Clear to Q 8 13 ns Clear to Q 13.5 16 ns Preset to Q 8 14 ns Preset to Q 13.5 17 ns Preset to Q CL = 15 pF Min 75 6 Max CL = 50 pF Min 65 9 Max MHz ns Units Clear to Q 6 9 ns Clock to Q or Q 9 14 ns 3 www.fairchildsemi.com DM74S74 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A www.fairchildsemi.com 4 DM74S74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
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